Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having a level shifter circuit.
Generally, semiconductor ICs (e.g., semiconductor memory devices) are not supplied with all operating voltages from the outside, but rather are supplied with only typical operating voltages, such as a power supply voltage (VDD), a ground voltage (VSS), etc. Therefore, semiconductor ICs may be provided with internal voltage generators to generate various levels of driving voltages.
In semiconductor ICs, the voltage swing levels may be different from one another within blocks that perform the same function. Specifically, the swing level of an input signal may be different from that of an output signal.
In this regard, a circuit configured to shift a swing level of an input signal is commonly referred to as a level shifter. A level shifter may be used to lower the swing level of an input signal, and is also widely used to boost the voltage level of an input signal. A semiconductor memory device may include a level shifter configured to shift the swing level of a signal swinging between a ground voltage (VSS) and a power supply voltage (VDD) and output a signal swinging between a ground voltage (VSS) and a high voltage (VPP).
FIG. 1 illustrates a conventional level shifter circuit.
Referring to FIG. 1, the conventional level shifter circuit includes an inverter INV1, an NMOS transistor TN1, an NMOS transistor SN1, a PMOS transistor TP1, a PMOS transistor TP2, and an inverter INV2. The inverter IV1 is configured to invert an input signal IN. The NMOS transistor TN1 has a gate connected to an output terminal A1 of the inverter INV1, a source connected to a ground voltage (VSS) terminal, and a drain connected to a node A3. The NMOS transistor SN1 has a gate connected to a power supply voltage (VDD) terminal, a source connected to a node A1, and a drain connected to a node A2. The PMOS transistor TP1 has a source connected to a high voltage (VPP) terminal, a drain connected to the node A2, and a gate connected to the node A3. The PMOS transistor TP2 has a source connected to the high voltage (VPP) terminal, a drain connected to the node A3, and a gate connected to the node A2. The inverter INV2 is configured to invert a signal of the node A3 and output the inverted signal as an output signal OUT.
The inverter INV1 uses the power supply voltage VDD as its pull-up voltage, and the inverter INV2 uses the high voltage VPP as its pull-up voltage. That is, the input signal IN swings between the ground voltage VSS and the power supply voltage VDD, and the output signal OUT swings between the ground voltage VSS and the high voltage VPP.
The operation of the conventional level shifter circuit will now be described briefly.
In one case, when the input signal IN has a logic high level (corresponding to the VDD level), the node A1 has the ground voltage (VSS) level. In this case, since the power supply voltage (VDD) level is applied to the gate of the NMOS transistor SN1, the NMOS transistor SN1 is turned on. Thus, the node A2 approaches the ground voltage (VSS) level, and the PMOS transistor TP2 is turned on. Since the NMOS transistor TN1 is in a turned-off state, the node A3 has the high voltage (VPP) level, and the PMOS transistor TP1 is turned off, thereby preventing an increase in the voltage level of the node A2. The resulting output signal OUT has a logic low level (corresponding to the VSS level).
On the other hand, when the input signal IN has a logic low level (corresponding to the VSS level), the node A1 has the power supply voltage (VDD) level. As a result, the NMOS transistor TN1 is turned on so that the node A3 is discharged. When the voltage level of the node A3 drops below the threshold voltage (Vt) of the PMOS transistor TP1, the PMOS transistor TP1 is turned on and drives the node A2 to the high voltage (VPP) level. Since the NMOS transistor SN1 is in a turned-off state, the PMOS transistor TP2 is turned off when the voltage level of the node A2 increases above the threshold voltage, thereby preventing the increase in the voltage level of the node A3. The resulting output signal OUT has a logic high level corresponding to the high voltage (VPP) level.
Meanwhile, since the high voltage VPP is applied to the PMOS transistors TP1 and TP2, the PMOS transistors TP1 and TP2 are implemented with thick transistors, which have a large gate insulation film thickness (Tox), in order to guarantee the reliability of the semiconductor device. The NMOS transistor SN1 is implemented with a slim transistor, which has excellent current driving capability and a low threshold voltage. Since the high voltage VPP may be applied to the drain of the NMOS transistor TN1, the NMOS transistor TN1 is also implemented with a thick transistor, which has a large gate insulation film thickness (Tax).
In the case of DRAMs, there is no great difference in the versions of the DRAMs. However, the power supply voltage (VDD) level tends to be gradually lowered in order to meet the low power requirement. Specifically, the power supply voltage (VDD) level has been lowered as the version of DRAMs have evolved (e.g., DDR1 (2.5 V), DDR2 (1.8 V), DDR3 (1.5 V), DDR4 (1.2 V-1.0 V)). However, there has been almost no difference in the high voltage (VPP) level, which has been in a range of 3.3 V to 3.0 V.
Such a trend towards a dropping power supply voltage VDD and an increasing high voltage VPP causes unstable operation of the level shifter circuit as illustrated in FIG. 2. FIG. 2 is a timing diagram showing input/output waveforms of the conventional level shifter circuit of FIG. 1 in a low power supply voltage environment (e.g., VDD=0.94 V) for various voltage levels of high voltage VPP. It is clear from FIG. 2 that the operation slows down when the level shifter circuit is enabled, and the voltage level is not fully pulled down to the ground voltage VSS when the level shifter circuit is disabled.
This result occurs for the following reason. The NMOS transistor TN1, which is configured to pull down the output node A3 of the conventional level shifter circuit, has a large gate insulation film thickness and a high threshold voltage. Therefore, as the logic high level (corresponding to the VDD level) of the node A1 is lowered, a longer time is taken to turn on the NMOS transistor TN1 so that the output node A3 is discharged to the ground voltage (VSS) level. When the power supply voltage (VDD) level drops even further, the current driving capability of the NMOS transistor TN1 becomes lower than that of the PMOS transistor TP2. As a result, the output node A3 fails to be sufficiently driven to the ground voltage (VSS) level.
Meanwhile, when the input signal IN having a logic low level is inputted in an environment where the power supply voltage VDD drops gradually, the logic level of the node A1 changes to a logic high level and a voltage equivalent to the power supply voltage minus the threshold voltage (VDD−Vt) is applied to the node A2. The lowered gate voltage of the NMOS transistor TN1 (also the voltage of node A1) reduces the amount of current flowing through the NMOS transistor TN1. Therefore, due to the operations of the PMOS transistors TP1 and TP2, which are cross-coupled to pull up the output node A3 to the high voltage (VPP) level, the output node A3 cannot be fully pulled down to a logic low level. Hence, the operation of charging the node A2 to the high voltage (VPP) level is hindered. This increases the delay in which the output node A3 changes from the high voltage (VPP) level to the ground voltage (VSS) level, and also increases the delay until the output signal OUT changes from the transition time point of the input signal IN. When the low power supply voltage (VDD) environment is severe, the amount of change of the output node A3 when the NMOS transistor TN1 is turned on becomes too small to control the PMOS transistor TP1. In this case, since the node A2 also fails to change from a logic low level to a high voltage (VPP) level, the PMOS transistor TP2 fails to be turned off. Thus, the output node A3 fails to change to a level which is recognizable as a logic low level. Consequently, the output signal OUT does not have a required output level.
FIG. 3 illustrates another conventional level shifter circuit.
The level shifter circuit of FIG. 3 is designed to overcome the above-mentioned concerns regarding the level shifter circuit of FIG. 1 which occur in the low power supply voltage (VDD) environment. Compared with the level shifter circuit of FIG. 1, the level shifter circuit of FIG. 3 further includes an inverter INV11 and MOS transistors TN11, TN12, TN13, and TN14, and the gate insulation film thicknesses of some transistors are modified.
For reference, PMOS transistors TP11 and TP12 and NMOS transistors TN11, TN12, TN13, and TN14 are implemented with thick transistors having a large gate insulation film thickness, and NMOS transistors SN11 and SN12 are implemented with slim transistors.
Since the basic operation of the level shifter circuit of FIG. 3 is substantially identical to that of the level shifter circuit of FIG. 1, a description thereof will be omitted for conciseness.
The proposed level shifter circuit may address the above-mentioned operational concerns of the level shifter circuit of FIG. 1 which occur in the low power supply voltage (VDD) environment, but is its circuit area is at least doubled by the increase in the number of transistors used therein. In addition, when the NMOS transistors TN13 and TN14 are turned on, the high voltage VPP is applied to the NMOS transistors SN11 and SN12 which are implemented with the slim transistors. This may degrade the reliability of the semiconductor device.